Substrate Noise Coupling, its Impact and Remedies in Mixed-Signal ICs

Substrate Noise Coupling, its Impact and Remedies in Mixed-Signal ICs

The demand on system on chip "SOC" and system in package "SIP" is increasing drastically to implement low cost, low power and small die size products.

The number of digital content is increasing in the presence of analog/RF and low power circuitry to achieve "SOC". The increased number of digital gates is accompanied by the introduction of multi clock domains that can fulfill the signaling requirement. Such environment generates tremendous amount of interference signals that can couple to the analog/RF and other sensitive parts of the SOC, and in the presence of a scaled down supply voltage (to cope with the scaled geometry) the analog/RF become even more sensitive to noise, in addition, the noise margins of the digital gates are also decreased. Signal isolation, especially between the digital and analog regions of the chip, is an increasing challenge for deep submicron technologies due to the increased integration complexity. In such an environment, noise disturbances generated by high switching rates of digital circuits and the presence of strong interference signals between tightly coupled channels can propagate through the common silicon substrate due to the finite conductivity and permittivity of the substrate material and couple to circuits located in different parts of the substrate.

The course covers modeling and design techniques for substrate noise coupling effects in SOCs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SOCs. The course covers measurements techniques, a set of design guide of noise isolation structures.

Currently Scheduled Course Dates

  • Jan 27, 2011 - Austin, TX
  • Jan 28, 2011 - Dallas, TX

What you'll learn from this course

  • How does noise propagate through different types of substrates
  • Types of Isolation structures and how to use them to minimize coupling
  • A series of design Guides to remedy the substrate noise impact
  • How a transceiver is tested at the block level and as a system
  • Case studies on the impact of Substrate coupling and its remedies in systems, circuits and devices

Course Prerequisites and Target Audience

  • A basic understanding of circuit design and SOC systems is the only pre-requisite for this course.

Course Overview

  • Analysis of Substrate Noise Coupling
    • Process Regions
    • Process Cross Sections
    • Connection of Devices to the Substrate
    • Noise Coupling Mechanism
    • Substrate Doping Profile Tradeoffs
    • Substrate Model Extraction in the IC Design Flow
    • Doping Profile Considerations
    • Substrate Model Extraction Kernels
  • Calibrating the Design Flow
    • Baseline Isolation
    • Effect of p-Guard Ring on Isolation
    • Effect of n-Guard Ring on Isolation
    • Effect of Deep n-Well on Isolation
    • Effect of Deep Trench on Isolation
    • De-embedding
  • Design Guide for Substrate Noise Isolation in SOC Applications
    • Isolation in Low Resistivity Substrate
    • Isolation vs. Frequency for Different Isolation Structures
    • Effect of Back Plane Connection on the Noise Isolation
  • On Chip Inductors Design Flow
    • Integrated Inductors
    • Inductor Design Flow
    • Analytical Exploration of the Design Space
    • Inductor Model and Substrate Parasitics
    • Calibrating the Field Solver
    • Model Fit
    • DFM Effects
  • Case Studies for the Impacts and Remedies of Substrate Noise Coupling .
    • System Level Case Study
    • Block Level Case Study
    • Device Level Case Study

Sample slides

Who Should Attend

  • Engineers seeking to understand fundamental SOC designs issues relating to clock coupling and signal integrity.
  • Engineers involved in board-level, circuit-level or system-level design of wireless or wireline systems.
  • Test engineers and technicians involved in noise and jitter measurement.
  • Engineers designing PLLs systems or subsystems such as voltage-controlled oscillators (VCOs) or reference oscillators (e.g. crystal oscillators)
  • Application and product engineers supporting customers in areas relating to frequency generation. Digital module design engineers
  • Engineers owning SOC floor planning and chip design

Course Materials

  • A hardcopy of the "Presentation materials" including numerous examples will be included as part of the course.

Instructor's Profile: Prof. Ahmed Helmy

Ahmed Helmy received his Bachelor degree in electrical and electronics engineering from Ain Shams University Cairo Egypt in 1994, masters in engineering physics and mathematics 1999 from the same University. He received his Ph.D. degree in RF circuit design and substrate noise coupling from the Ohio state university in 2006 electrical and computer engineering department. On the industrial level he joined Mentor Graphics Co. in 1996 where he worked for 4 years in macro modeling and behavioral modeling for RF circuits and systems as well as statistical modeling and DFM simulations. He joined Intel Corporation in Arizona in 2002 as an RF circuit designer. Currently he is a staff design engineer with Intel Corporation working in high speed IO circuits and process technologies that support such applications. He is also an Associate Professor with Arizona State University since 2008, teaching advanced Analog design. He has 3 pending US patents, several publications and a book on substrate noise coupling in RFICs. He serves as a reviewer for several IEEE conferences and journals.

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