DFT Beyond Scan

DFT Beyond Scan

This course is a survey of some of the big tools in the DFT engineers' tool belt. You'll get the why and the how of things like scan, functional tests, memory BIST, logic BIST, and JTAG. We'll talk about and analyze the cost benefits of these test techniques and identify product situations where they represent a positive ROI.

Currently Scheduled Course Dates

  • Jan 13, 2011 - Dallas, TX
  • Jan 14, 2011 - Austin, TX

What you'll learn from this course

You will take away a comprehensive knowledge of the pillars of DFT. You will understand the benefits of scan not only for manufacturing test but also for burnin, debug, and bring up efforts. You will understand the value of Built-In Self Test techniques and when they are cost appropriate to use. You will get an up close bit-banging look at JTAG and why is has become the sweetheart of the DFT world. This knowledge will enable you to step up and become the DFT architect; making the decisions for test, burnin, and debug resources that make a chip testable and debuggable for the right cost.

Course Prerequisite

  • Participants should be familiar with the basics of front end chip design; RTL and verification through synthesis.

Overview of the course

  • Scan chains...now that I've got 'em what can I do with 'em?
  • ATPG compression. What is it and who cares?
  • An in-depth look at Memory BIST. Costs, benefits and appropriate use scenarios.
  • An in-depth look at Logic BIST. Costs, benefits and appropriate use scenarios.
  • An in-depth look at JTAG (IEEE 1149.1 and 1149.6)

Sample slides

Who Should Attend

  • Novice and intermediate DFT engineers who wish to expand their knowledge of the field.
  • Product and Test Engineers who want to migrate "upstream" into design.
  • Design and verification engineers who are looking to move over into DFT.
  • EE/CS Graduate Students planning to work in the semiconductor industry

Course Materials

  • A hardcopy of the "Presentation materials" will be included as part of the course.

Instructor's Profile: Dr. Molyneaux

Dr. Molyneaux was the principal DFT architect for the world-class family of PowerPC chips at the Somerset Design Center, as well as the paradigm changing SUN Microsystems Niagara family of multi-core, multi-threaded processors.

With more than 20 published papers, patents and patents pending, Bob has the insight and experience to be a highly effective teacher of DFT tools, techniques and methods.

 
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